1. Field
The present invention relates to the field of electronics. More specifically, the invention relates to an apparatus and method for detecting and handling self-modifying code conflicts.
2. General Background
Early microprocessors featured circuitry arranged to successively fetch and execute instructions. More specifically, each instruction pointer (IP), identifying a line of memory in which an instruction is stored, is fetched and placed in an instruction fetch pipeline. The instruction fetch pipeline is comprised of a number of processing stages in which the first few processing stages are referred to as a xe2x80x9cfront-end pipelinexe2x80x9d and remaining processing stages are referred to as a xe2x80x9cback-end pipelinexe2x80x9d. Since xe2x80x9cin-flightxe2x80x9d IPs are loaded into the front-end pipeline where instructions associated with these IPs are subsequently executed at the back-end pipeline, the in-flight IPs are subject to self-modifying code (SMC) conflicts.
A xe2x80x9cSMC conflictxe2x80x9d is a condition where the execution of an instruction of an executable program causes self-modification of that executable program. This self-modification may lead to the execution of xe2x80x9cstalexe2x80x9d data. In particular, a SMC conflict may occur for a number of reasons including, for example, those instances when a new instruction is created or when data embedded into the instruction of a repeatedly executed program is modified. Thus, various SMC handling techniques have been adopted.
Over the last few years, SMC conflicts have been handled through a variety of techniques. For example, for the i80486(trademark) microprocessor produced by Intel Corporation of Santa Clara, Calif., a branch instruction was coded to follow a write instruction to program memory. This branch instruction caused the entire instruction pipeline to be flushed. Unfortunately, the insertion of branch instructions tends to be extremely inefficient, especially for pipelined processors since a complete pipeline flush would invalidate information stored in several queues.
With respect to the PENTIUM(copyright) microprocessor, the branch instruction technique was not utilized; instead, each in-flight instruction associated with a SMC conflict is detected and marked since the pipeline had only a few stages. The marked instruction is passed to an execution stage of the pipeline, at which time, the pipeline and those queues on the pipeline are flushed.
Another technique, utilized by the PENTIUM(copyright) PRO microprocessor, requires the use of an instruction victim cache (IVC) in combination with a normal instruction cache (I-cache) to guarantee that all of the instructions in the pipeline would be resident in one of these caches. However, management logic of these caches would unnecessarily complicate the cache architecture of the microprocessor and would provide a less than optimal solution for SMC conflict detection.
Hence, it would be advantageous to provide an apparatus, system and method to detect and clear SMC conflicts associated with the front-end portion of an instruction fetch pipeline and to provide a scheme after the occurrence of the SMC conflict to regain synchronization of the multiple front-end pipelines to each other.
Briefly, in one embodiment, a method is described for detecting and recovering from self-modifying code conflicts. The method comprises comparing an address with information progressing through a front-end pipeline of an instruction pipeline. If the address compares with information progressing through the front-end pipeline, a selection portion of the information is invalidated.